1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2009-124141, filed May 22, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
A semiconductor device having a BGA (Ball Grid Array) structure has been known. A semiconductor chip is mounted on a semiconductor substrate such as a wiring substrate having wiring patterns that are formed on one surface thereof Japanese Unexamined Patent Application, First Publication, No. JP-A-2001-044229 discloses such a semiconductor device. The semiconductor device has a BGA structure. The semiconductor device includes predetermined circuits on one surface of the wiring substrate. The semiconductor device includes a semiconductor chip having plural electrode pads mounted on the surface of the wiring substrate. A matrix array of solder balls is disposed on the other surface of the wiring substrate. Solder balls serve as external electrodes that correspond to the electrode pads on the semiconductor chip. The electrode pads on the semiconductor chip and the corresponding external electrodes are electrically connected to each other via wires of the wiring substrate. A sealing member is disposed on one surface of the wiring substrate. The sealing member covers at least connection portions between the semiconductor chip and the wiring substrate.
The semiconductor device having the past BGA structure can be manufactured by an MAP (Mold Array Process) for manufacturing plural products at a time.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-133521 discloses that to decrease the thickness of the semiconductor device, there was suggested a semiconductor device having the BGA structure using a wiring substrate having an opening. Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-133521 discloses the semiconductor device configured to dispose a semiconductor chip in the opening of the wiring substrate by the use of a support tape. This configuration provides a clearance between the semiconductor devices. This configuration allows stacking the semiconductor devices having the BGA structure with reduced stress applied to the connecting portions between the semiconductor devices.
The semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2001-044229 has the following issues. The semiconductor chip is bonded and fixed to the wiring substrate through a DAF (Die Attach Film) or an adhesive. When a material having a different coefficient of thermal expansion is bonded and fixed to the wiring substrate, stress is generated in the semiconductor device in manufacture, and this stress is applied to the external electrodes. The external electrodes may be broken due to this stress.
The semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-133521 discloses the following problems. The balance of thermal expansion is poor between the support tape disposed on one surface of the wiring substrate and the sealing member disposed on the other surface thereof, and stress or bending may be caused in the semiconductor device. When stress or bending is caused, disconnection may be caused at the time of mounting the semiconductor device on a main substrate or the like. The external electrodes are not partially connected. Particularly, in the semiconductor device having plural semiconductor devices stacked, bending or stress of each of the stacked semiconductor devices has a great influence. In the related art, the reliability of secondary mounting is lowered due to the generation of stress or bending of each of the stacked semiconductor devices.